V-Tec AT16/C5 Especificaciones Pagina 10

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Si2400
10 Rev. 1.3
2. Typical Application Schematic
Z1
R1 5
Refer to AN48 for Layout Guidelines
Please submit layout to Silicon Labs
for review prior to PCB fabrication.
+
C5
D4
Note 5 : R27, R28, D3, D4, Z4, Z5, RV 2 may be populated for enhanced lightning option.
C8
C13
C4
R7
R31
RV 1
FB1
GPIO3/ESC
AOUT
TI P
C22
C19
RXD
RESET_
R8
R9
R13
C9
C26
C3
Note 6 : L1,L2, C38, C39, R31, R32 are for EN55022/CISPR-22 Conducted Disturbance compliance.
D3
L1
R26
R12
U1
Si2400
1
2
3
4
5
6
7
89
10
11
12
13
14
15
16
XT ALI
XT ALO
CLKOUT
VD
RXD
TXD
CTS
RESET AOUT
GPIO4
C1A
GND
ISOB
GPIO3
GPIO2
GPIO1
Q2
C16
R18
R25
R2
+
C12
Z5
D1
R1 1
C20
C39
R1 9
Q1
C18
C10
RING
R5
+
C14
Decoupling cap for U1 VD
Note 3 : See "Billin g Tone Immunity" sectio n for optional billing tone filter (Germany , Switzerland, Sout h Africa) .
FB2L2
R32
Q3
U2
Si3015
1
2
3
4
5
6
7
89
10
11
12
13
14
15
16
TST A/QE2
TSTB/DCT
IGND
C1B
RNG1
RNG2
QB
QE VREG
NC/VREG2
NC/REF
DCT/REXT2
REXT
RX
NC/FI LT
TX/FI LT 2
C30
R6
C7
RV 2
C1
GPIO2/CD_
Note 1 : R12, R13 and C14 are only require d if complex AC termination is used (ACT bit = 1).
GPIO4/ALER T
Note 2 : See "Ringer Impedance" sectio n for optional Czech Republic support.
R1 7
C24
R28
Q4
VCC
Y1
12
R24
TXD
C38
C27
Note 4 : See Appendix for applications requiring UL 1950 3rd edition compliance.
CLKOUT
R10
R1 6
D2
R27
Z4
C6
CTS_
C25
GPIO1/EOFR
Figure 3. Typical Application Circuit Schematic
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