V-Tec AT16/C5 Especificaciones Pagina 67

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Si2400
Rev. 1.3 67
Reset settings = 0000_0000
b
(0x00)
SE4 (CF5). Chip Functions 5
BitD7D6D5D4D3D2D1D0
Name
NBCK SBCK DRT GPE APO TRSP
Type R R R/W R/W R/W R/W
Bit Name Function
7NBCK9600 Baud Clock (Read Only).
6 SBCK 600 Baud Clock (Read Only).
5:4 DRT Data Routing (See Figure 10).
00 = Data mode, DSP output transmitted to line, line received by DSP input.
01 = Voice mode, selected AIN transmitted to line, line received by AOUT.
10 = Loopback mode, RXD through microcontroller (DSP) to TXD. AIN looped to AOUT.
11 = Codec mode, data from DSPOUT to AOUT, AIN to DSPIN.
3 GPE*
GPIO1 Enable.
0 = Disable.
1 = Enable GPIO1 to be HDLC end-of-frame flag.
2 Reserved Read returns zero.
1 APO
Analog Power On.
0 = Disable.
1 = Power on analog ADC and DAC.
0TRSP*
TXD2/RXD2 Serial Port.
0 = Disable.
1 = Enable TXD2/RXD2 serial port so that RXD2 is GPIO1 and TXD2 is GPIO2.
*Note: GPE and TRSP are mutually exclusive. Only one can be set at any one time, and they override the settings in registers
GPIO2 and GPIO1. Once TXD2 and RXD2 are enabled through TRSP
= 1
b
, the primary serial port TXD and RXD no
longer function and pins TXD2 and RXD2 control the Si2400. This feature allows a second microcontroller to control
the Si2400.
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